Chapter#3 - THE PIC ASSEMBLY LANGUAGE PROGRAMMING AND ARCHITECTURE

Upon Completion of this chapter, You will be able to:

• Examine the data RAM file register of the PIC micro-controller
• Manipulate data using the WREG and MOV instruction
• Perform simple operations such as DD and MOVE using the file register and access bank in the PIC micro-controller
• Explain the purpose of the status register
• Discuss data RAM memory space allocation in the PIC micro-controller
• List Special function registers of the PIC micro-controller
• Code simple PIC Assembly Language instructions
• Describe PIC data types and directives
• Assemble and run a PIC program using MPLAB
• Describe the sequence of events that occur upon PIC power-up
• Examine programs in PIC ROM code
• Explain the PIC ROM memory map
• Detail the execution of PIC Assembly language instruction
• Understand the RISC and Harvard architectures of the PIC micro-controller
• Examine the PIC's registers and data RAM using the MPLAB simulator

SECTION  I - THE WREG , MOVLW, ADDLW IN THE PIC

• SECTION  I-1: The WREG Register in the PIC micro-controller
• SECTION  I-2: The MOVLW instruction in the PIC micro-controller
• SECTION  I-3: The ADDLW instruction in the PIC micro-controller

SECTION  II - FILE REGISTER IN THE PIC MICRO-CONTROLLER

• SECTION  II-1: File register (Data RAM) Space Allocation in PIC micro-controller
• SECTION  II-2: Special Function Registers SFR's in PIC micro-controller
• SECTION  II-3: General-Purpose Registers or RAM in PIC micro-controller
• SECTION  II-4: General Purpose Registers RAM Vs EEPROM in PIC micro-controller
• SECTION  II-5: File Register and Access bank in the PIC18

SECTION  III: INSTRUCTION WITH THE DEFAULT ACCESS BANK

• SECTION  III-1: MOVWF Instruction in the PIC micro-controller
• SECTION  III-2: Instructions involving the WREG and the Access Bank
• SECTION  III-3: ALU Instructions Using Both WREG and FileReg
• SECTION  III-4: File Register Instructions Using FileReg or WREG and Destination
• SECTION  III-5: The COMF Instruction in the PIC micro-controller
• SECTION  III-6: DECF Instruction in the PIC micro-controller
• SECTION  III-7: MOVF Instruction in the PIC micro-controller
• SECTION  III-8: MOVFF Instruction in the PIC micro-controller

SECTION  IV: THE STATUS REGISTER IN PIC MICRO-CONTROLLER

• SECTION  IV-1: Bits of PIC Status Resister
• SECTION  IV-2: ADDLW Instruction and the Status Register
• SECTION  IV-3: Instructions That Affect Flag Bits
• SECTION  IV-4: Flag Bits and Decision Making

SECTION  V: PIC DATA FORMAT AND DIRECTIVES

• SECTION  V-1: Data Format Representation Hex Numbers
• SECTION  V-2: Data Format Representation Binary Numbers
• SECTION  V-3: Data Format Representation Decimal Numbers
• SECTION  V-4: Data Format Representation ASCII Character
• SECTION  V-5: Assembler Directives EQU - Equate
• SECTION  V-6: Assembler Directives SET
• SECTION  V-7: Using EQU for Fixed Data Assignment
• SECTION  V-8: Using EQU for SFR Address Assignment
• SECTION  V-9: Using EQU for RAM Address Assignment
• SECTION  V-10: ORG - Origin, END, LIST, #include, _config, radix Directives
• SECTION  V-11: Rules for Labels in Assembly Language
• SECTION  V-12: Using EQU for RAM Address Assignment

SECTION  VI: INTRODUCTION TO PIC ASSEMBLY PROGRAMMING

• SECTION  VI-1: Introduction to PIC Assembly Programming
• SECTION  VI-2: Structure of Assembly Language
• SECTION  VI-3: Assembling and Linking a PIC Program
• SECTION  VI-4: asm, err, and Object Files in PIC
• SECTION  VI-5: "lst" and "map" Files in PIC
• SECTION  VI-6: The Program Counter and Program ROM Space in PIC
• SECTION  VI-7: ROM Memory map in the PIC18 Family
• SECTION  VI-8: Where the PIC Wakes Up when it is Powered Up
• SECTION  VI-9: Placing Code in Program ROM
• SECTION  VI-10: Executing a Program Byte by Byte
• SECTION  VI-11: ROM Width in the PIC18
• SECTION  VI-12: Harvard Architecture in the PIC
• SECTION  VI-13: Instruction Size of the PIC18 MOVLW Instruction Formation
• SECTION  VI-14: Instruction Size of the PIC18 ADDLW Instruction Formation
• SECTION  VI-15: Instruction Size of the PIC18 MOVWF Instruction Formation
• SECTION  VI-16: Instruction Size of the PIC18 MOVFF Instruction Formation
• SECTION  VI-17: Instruction Size of the PIC18 GOTO Instruction Formation
• SECTION  VI-18: Coming from other microprocessors to the PIC18
• SECTION  VI-19: The RISC Architecture in the PIC
• SECTION  VI-20: Features of RISC Architecture in the PIC
• SECTION  VI-21: Viewing Register and Memory With MPLAB Simulator

Basic Introduction of Chapter # 3

This Chapter will began with an exploration of the major registers of the PIC, including WREG, SFR's, and general-purpose data RAM, and the program counter. The use of these registers will be demonstrated in thr context of programming examples. The process of creating an assembly language program will be described from writing the source files, to assembling it, linking, and executing the program. The program counter register always points to the next instruction to be executed. The way the PIC uses program ROM space will be explored. PIC assembly language programmers must be aware of where programs are placed in ROM, and how much memory is available.

An assembly language program is composed of a series of statements that are either instructions or pseudo-instructions, also called directives. Instructions are translated by the assembler into machine code. Pseudo instructions are not translated into machine code. They direct the assembler in how to translate instructions into machine code. Some pseudo instructions, called data directives, are used to define data. Data is allocated in byte size increments. The data can be in a binary, hex, decimal, or ASCII formats.

Flags are useful to programmers because they indicate certain conditions, such as carry or zero, that result from execution of instructions. The concepts of RISC and Harvard architectures were also explored.

The RISC architecture allows the design of much more powerful micro controllers. It has a simple instruction set and uses of a large number of registers. Harvard architecture allows us to bring more code and data to the CPU faster. The use of a wider data in the PIC18 allows us to fetch an instruction every every cycle because the PIC instructions are typically 2 bytes.