SECTION VI-20: Features of RISC Architecture in the PIC

The following are some of the features of RISC as implemented by the PIC18 microcontroller.

  • RISC processors have a fixed instruction size. In a CISC microcontroller such as the 8051, instructions can be 1, 2, or even 3 bytes. Example below following instructions in the 8051:
CLR C ;Clear carry flag 1 byte instruction
ADD Accumulator, #mbyte   2 byte instruction
LJMP target_address   3 byte instruction


  • This variable instruction size makes the task of the instruction decoder very difficult because the size of the incoming instruction is never known. In a RISC architecture, the size of all instructions is fixed. Therefore, the CPU can decode the instructions quickly, This is like a bricklayer working with bricks of the same size as opposed to using bricks of variable sizes. It is much more efficient to use bricks of the same size.


  • One of the major characteristics of RISC architecture is a large number of registers. All RISC architectures have at least 32 registers. Of these 32 registers, only few are assigned to a dedicated function. One advantage of a large number of registers is that it avoids the need for a large stack to store parameters. A stack can be implemented on a RISC processor, it is not as essential as in CISC because so many registers are available. In the PIC micro-controllers the use of a 256 byte bank for the file register satisfies this RISC feature


  • RISC processors have a small instruction set. RISC processors have only the basic instructions such as ADD, SUB, MUL, LOAD, STORE, AND, OR, EXOR, CALL, JUMP etc. The limited number of instructions is one of the criticisms leveled at the RISC processor because it makes the job of assembly language programmers much more difficult compared to the job of CISC assembly language programming. RISC is more used in high-level language environments such as C programming language rather than assembly language programming environments. Some defenders of CISC have called it "Complete Instruction Set Computer" instead of "Complex Instruction Set Computer", because it has a complete set of every kind of instruction. How many of these instructions are used and how often is another matter. The limited number of instructions in RISC leads to programs that are large and these programs can use more memory. Memory is cheap so memory is not a problem. Before the advent of semiconductor memory in the 1960s, CISC designers had to pack as much action as possible into a single instruction to get the maximum bang for their buck. In the PIC16 we have around 35 instructions, while the PIC 18 has 75 instructions.


  • With all the difficulties with the RISC programming, what is the gain?, The most important characteristics of the RISC processor is that more than 95% of instructions are executed with only one clock cycle, in contrast to CISC instructions. Some of the 5% of the RISC instructions that are executed with two clock cycles can be executed with one clock cycle by juggling instructions around (code scheduling). Code scheduling is most often the job of the compiler.


  • RISC processors have separate buses for data and code. In all the x86 processors, like all other CISC computers, there is one set of buses for the address. example A0 - A24 in the 80286 and another set of buses for data, example D0 - D15 in the 80286, carrying opcode and operands in and out of the CPU. To access any section of memory, whether it contains code or data operands, the same address bus and data bus are used. In RISC processors, there are 4 sets of buses as follows:
  1. Set of data buses for carrying data (operands) in and out of the CPU.
  2. Set of address buses for accessing the data.
  3. Set of buses to carry the opcodes and data operands
  4. Set of address buses to access the opcodes.

The use of separate buses for code and data operands is commonly referred to as Harvard architecture.


  • CISC has a large number of instructions, each with so many different addressing modes, micro instructions (microcode) are used to implement them. The implementation of micro instructions inside the CPU takes more then 40 - 60% of transistors in many CISC processors. In the case of RISC, due to the small set of instructions, they are implemented using the hardwire method. Hardwiring of RISC instructions takes no more than 10% of the transistors.


  • RISC used load / store architecture. In CISC microprocessors, data can be manipulated while it is still in memory. For example, in instructions such as "ADD Reg, Memory", the microprocessor must bring the contents of the external memory location into the CPU, add it to the contents of the register, then move the result back to the external memory location. The problem is there might be a delay in accessing the data from external memory. Then the whole process would be stalled, preventing other instructions from proceeding in the pipeline. In RISC, the instructions can only load from external memory location into registers or store registers into external memory locations. There is no direct way of doing arithmetic and logic operations between a register and the contents of external memory locations. All these instructions must be performed by first bringing both operands into the registers inside the CPU, then performing the arithmetic or logic operation, and then sending the result back to memory. This idea is referred to as load / store architecture. The arithmetic and logic operations are between the fileReg (an internal memory) and WREG, but none involve a ROM location and a fileReg location. For example: there is no "ADDW ROM-Loc" instruction in PIC18. In recent years, CISC processors such as Pentium have used some of the RISC features in their design. This is the only way they could enhance the processing power of the x86 processors and stay competitive. Of course, they had to use lots of transistors to do the job, because they had to deal with all the CISC instructions of the 8086/286/386 processors and the legacy software of DOS.




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